Metal-Oxide Semiconductor Field Effect Transistors (“MOSFETs”) are a common type of power switching device. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure provided adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer. When a voltage of sufficient strength is applied to the gate structure to place the MOSFET device in an on state, a conduction channel region forms between the source and drain regions thereby allowing current to flow through the device. When the voltage that is applied to the gate is not sufficient to cause channel formation, current does not flow and the MOSFET device is in an off state. As those skilled in the art are aware, MOSFETs can be P-channel field effect transistors, N-channel field effect transistors, depletion mode devices, etc.
To reduce costs by making smaller geometry semiconductor devices and to improve performance, semiconductor component manufacturers have developed techniques in which the gate structures of field effect transistors, isolation regions, and deep contacts into the silicon are manufactured in trenches. The trenches are made at the minimum capable geometry of the photolithography equipment to minimize space and to minimize the amount of material needed to fill and etchback the trench openings. Because the trenches are at their minimum feature size, making contact to them is difficult. Typically, contacts are made using a masking step that leaves trench-fill material behind as a contact opening trench stop pad. Drawbacks with this approach include increased cost of the semiconductor components, increased sizes of the chips or dice from which semiconductor components are made, and, for wider trench geometries, increased topography of the semiconductor chips because of the increased amount of material left behind.
Accordingly, it would be advantageous to have a semiconductor component having a contact landing pad and a method for manufacturing the contact landing pad that is suitable for small geometry semiconductor devices. It would be of further advantage for the semiconductor component to be cost efficient to manufacture.